With the development of miniaturization of semiconductors, the degree of integration of semiconductor integrated circuits has been increased. As a result, a semiconductor having thereon a plurality of processors becomes more likely to be realized.
FIG. 1 schematically illustrates by way of example a system wherein CPUs which are provided on a semiconductor circuit are concurrently subjected to a screening test performed by a test apparatus outside of the semiconductor circuit. This system has a configuration wherein scan-in signals 300-1 to 300-n are input from scan test apparatus 6 to respective CPUs 10-1 to 10-n that are provided on semiconductor integrated circuit 5, and scan-out signals 302-1 to 302-n are output from respective CPUs 10-1 to 10-n to scan-test apparatus 6.
In this configuration, scan test apparatus 6 sets scan data that are to be used for performing screen testing of flip flop circuits in the CPUs by means of scan-in signals 300-1 to 300-n, and acquires the executed test results by means of scan-out signals 302-1 to 302-n. The executed test results thus acquired are then compared with comparative data that are computed by a simulator etc. If any of the executed test results differ from the comparative data, then semiconductor integrated circuit 5 is discarded.
Thus, scan test apparatus 6 has the capability to concurrently perform a screening test of CPUs.
However, the system shown in FIG. 1 suffers from the following drawbacks. Since the time required to conduct screen testing of a semiconductor integrated circuit is determined by the time needed to set scan data that is to be used for conducting screen testing of flip-flop circuits in a single CPU, the speed of the screening test is very slow. Further, since a scan-in signal and a scan-out signal must be separately connected to the all CPUs, the hardware cost is high.
As a technique to address these problems, a circuit that uses a plurality of CPU cores is described in Patent literature 1. Patent literature 1 discloses a circuit wherein all latches in each CPU core are connected in a scan chain manner, similar to the configuration of the system shown in FIG. 1. Accordingly, Patent literature 1 suffers from the drawbacks similar to those that the system shown in FIG. 1 suffers from.
FIG. 2 illustrates a typical example of a system in which testing of a single CPU is accelerated. The example shown in FIG. 2 comprises comparative test apparatus 8 for performing a comparative test on CPU 10 in semiconductor integrated circuit 5 utilizing test program 71 and test operation result 72 that are stored in memory 7.
In such a configuration, CPU 10 executes test program 71 through memory bus 4, and loads the execution result into test operation result 72. Comparative test apparatus 8 then acquires test operation result 72 through comparative test apparatus signal 400 and performs a check to determine whether or not the CPU has operated properly.
This allows an extremely high speed test of a single CPU using a real speed operation. As a result, speeding up the screening test of semiconductor integrated circuits having a plurality of CPUs is also achieved.
However, the system shown in FIG. 2 has the following drawbacks.
Since CPU 10 is tested using only test operation result 72 that is stored in memory, the test coverage is very small.
Further, in order to prepare data that can be compared with test operation result 72, a large-scale simulation that covers real speed operations is required, thus making the system very costly.
As a technique to address these problems, Patent literature 2 discloses a method of testing the functions of a CPU, and a method of selecting a test program for the test. Therefore, Patent literature 2 suffers from the problems similar to those that the system shown in FIG. 2 suffers from.
Also, Patent literature 3 discloses a method of comparing output signals from a plurality of CPUs with one another to provide a self-diagnostic capability for a CPU. In this method, signals used for the comparison are CPU internal signals, such as writing data on a bus, address signals that are output from a control circuit, and a computing flag(s) that is/are output from a processor. Accordingly, Patent literature 3 suffers from the problem of an increase in the developing cost required for the reconstruction of the existing CPU because of the comparison of the internal signals. Patent literature 3 also suffers from a decrease in the test coverage because signals to be compared are computation results or memory access information alone, unlike the case in which the internal signals are compared with instruction execution information including the computation results or memory access information.
Patent literature 1: JP2006-153538A
Patent literature 2: JPH8-235023A
Patent literature 3: JPH6-161798A